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<span id="openzim-page-title" class="mw-page-title-main"><span class="mw-page-title-main">Hardware acceleration</span></span>

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</style><div role="note" class="hatnote navigation-not-searchable">For hardware accelerators in startup companies, see <a href="Seed_accelerator" class="mw-redirect" title="Seed accelerator">Seed accelerator</a>.</div>

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<p><b>Hardware acceleration</b> is the use of <a href="Computer_hardware" title="Computer hardware">computer hardware</a> designed to perform specific functions more efficiently when compared to <a href="Software" title="Software">software</a> running on a general-purpose <a href="Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU). Any <a href="Function_(mathematics)" title="Function (mathematics)">transformation</a> of <a href="Data_(computing)" class="mw-redirect" title="Data (computing)">data</a> that can be calculated in software running on a generic CPU can also be calculated in custom-made hardware, or in some mix of both.

</p><p>To perform computing tasks more efficiently, generally one can invest time and money in improving the software, improving the hardware, or both. There are various approaches with advantages and disadvantages in terms of decreased <a href="Latency_(engineering)" title="Latency (engineering)">latency</a>, increased <a href="Throughput" class="mw-redirect" title="Throughput">throughput</a>, and reduced <a href="Performance_per_watt" title="Performance per watt">energy consumption</a>. Typical advantages of focusing on software may include greater versatility, more rapid <a href="Software_development_process" title="Software development process">development</a>, lower <a href="Non-recurring_engineering" title="Non-recurring engineering">non-recurring engineering</a> costs, heightened <a href="Software_portability" title="Software portability">portability</a>, and ease of <a href="Software_release_life_cycle" title="Software release life cycle">updating features</a> or <a href="Patch_(computing)" title="Patch (computing)">patching</a> <a href="Software_bug" title="Software bug">bugs</a>, at the cost of <a href="Overhead_(computing)" title="Overhead (computing)">overhead</a> to compute general operations. Advantages of focusing on hardware may include <a href="Speedup" title="Speedup">speedup</a>, reduced <a href="Electric_energy_consumption" title="Electric energy consumption">power consumption</a>,<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> lower latency, increased <a href="Parallel_computing" title="Parallel computing">parallelism</a><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> and <a href="Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a>, and <a href="Circuit_underutilization" title="Circuit underutilization">better utilization</a> of area and <a href="Execution_unit" title="Execution unit">functional components</a> available on an <a href="Integrated_circuit" title="Integrated circuit">integrated circuit</a>; at the cost of lower ability to update designs once <a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">etched onto silicon</a> and higher costs of <a href="Functional_verification" title="Functional verification">functional verification</a>, times to market, and the need for more parts. In the hierarchy of digital computing systems ranging from general-purpose processors to <a href="Full_custom" title="Full custom">fully customized</a> hardware, there is a tradeoff between flexibility and efficiency, with efficiency increasing by <a href="Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">orders of magnitude</a> when any given application is implemented higher up that hierarchy.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> This hierarchy includes general-purpose processors such as CPUs,<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> more specialized processors such as programmable <a href="Shader" title="Shader">shaders</a> in a <a href="Graphics_processing_unit" title="Graphics processing unit">GPU</a>,<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> applications implemented on <a href="Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate arrays</a> (FPGAs),<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> and fixed-function implemented on <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuits</a> (ASICs).<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup>

</p><p>Hardware acceleration is advantageous for <a href="Computer_performance" title="Computer performance">performance</a>, and practical when the functions are fixed, so updates are not as needed as in software solutions. With the advent of <a href="Reconfigurable_computing" title="Reconfigurable computing">reprogrammable</a> <a href="Programmable_logic_device" title="Programmable logic device">logic devices</a> such as FPGAs, the restriction of hardware acceleration to fully fixed algorithms has eased since 2010, allowing hardware acceleration to be applied to problem domains requiring modification to algorithms and processing <a href="Control_flow" title="Control flow">control flow</a>.<sup id="cite_ref-BingFPGA_8-0" class="reference"><a href="#cite_note-BingFPGA-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ProjCatapult_9-0" class="reference"><a href="#cite_note-ProjCatapult-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> The disadvantage, however, is that in many open source projects, it requires proprietary libraries that not all vendors are keen to distribute or expose, making it difficult to integrate in such projects.

</p>

<div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2></div>

<p><a href="Integrated_circuit" title="Integrated circuit">Integrated circuits</a> are designed to handle various operations on both analog and digital signals. In computing, digital signals are the most common and are typically represented as binary numbers. <a href="Computer_hardware" title="Computer hardware">Computer hardware</a> and software use this <a href="Binary_representation" class="mw-redirect" title="Binary representation">binary representation</a> to perform computations. This is done by processing <a href="Boolean_function" title="Boolean function">Boolean functions</a> on the binary input, and then outputting the results for storage or further processing by other devices.

</p>

<div class="mw-heading mw-heading3"><h3 id="Computational_equivalence_of_hardware_and_software">Computational equivalence of hardware and software</h3></div>

<p>Because all <a href="Turing_machine" title="Turing machine">Turing machines</a> can run any <a href="Computable_function" title="Computable function">computable function</a>, it is always possible to design custom hardware that performs the same function as a given piece of software. Conversely, software can always be used to emulate the function of a given piece of hardware. Custom hardware may offer higher performance per watt for the same functions that can be specified in software. <a href="Hardware_description_language" title="Hardware description language">Hardware description languages</a> (HDLs) such as <a href="Verilog" title="Verilog">Verilog</a> and <a href="VHDL" title="VHDL">VHDL</a> can model the same <a href="Semantics_(computer_science)" title="Semantics (computer science)">semantics</a> as software and <a href="Logic_synthesis" title="Logic synthesis">synthesize</a> the design into a <a href="Netlist" title="Netlist">netlist</a> that can be programmed to an FPGA or composed into the <a href="Logic_gate" title="Logic gate">logic gates</a> of an ASIC.

</p>

<div class="mw-heading mw-heading3"><h3 id="Stored-program_computers">Stored-program computers</h3></div>

<p>The vast majority of software-based computing occurs on machines implementing the <a href="Von_Neumann_architecture" title="Von Neumann architecture">von Neumann architecture</a>, collectively known as <a href="Stored-program_computer" title="Stored-program computer">stored-program computers</a>. <a href="Computer_program" title="Computer program">Computer programs</a> are stored as data and <a href="Execution_(computing)" title="Execution (computing)">executed</a> by <a href="Processor_(computing)" title="Processor (computing)">processors</a>. Such processors must fetch and decode instructions, as well as <a href="Load%E2%80%93store_architecture" title="Load–store architecture">load data operands</a> from <a href="Computer_memory" title="Computer memory">memory</a> (as part of the <a href="Instruction_cycle" title="Instruction cycle">instruction cycle</a>), to execute the instructions constituting the software program. Relying on a common <a href="CPU_cache" title="CPU cache">cache</a> for code and data leads to the "von Neumann bottleneck", a fundamental limitation on the throughput of software on processors implementing the von Neumann architecture. Even in the <a href="Modified_Harvard_architecture" title="Modified Harvard architecture">modified Harvard architecture</a>, where instructions and data have separate caches in the <a href="Memory_hierarchy" title="Memory hierarchy">memory hierarchy</a>, there is overhead to decoding instruction <a href="Opcode" title="Opcode">opcodes</a> and <a href="Multiplexer" title="Multiplexer">multiplexing</a> available <a href="Execution_unit" title="Execution unit">execution units</a> on a <a href="Microprocessor" title="Microprocessor">microprocessor</a> or <a href="Microcontroller" title="Microcontroller">microcontroller</a>, leading to low circuit utilization. Modern processors that provide <a href="Simultaneous_multithreading" title="Simultaneous multithreading">simultaneous multithreading</a> exploit under-utilization of available processor functional units and <a href="Instruction-level_parallelism" title="Instruction-level parallelism">instruction level parallelism</a> between different hardware threads.

</p>

<div class="mw-heading mw-heading3"><h3 id="Hardware_execution_units">Hardware execution units</h3></div>

<p>Hardware execution units do not in general rely on the von Neumann or modified Harvard architectures and do not need to perform the instruction fetch and decode steps of an <a href="Instruction_cycle" title="Instruction cycle">instruction cycle</a> and incur those stages' overhead. If needed calculations are specified in a <a href="Register-transfer_level" title="Register-transfer level">register transfer level</a> (RTL) hardware design, the time and circuit area costs that would be incurred by instruction fetch and decoding stages can be reclaimed and put to other uses.

</p><p>This reclamation saves time, power, and circuit area in computation. The reclaimed resources can be used for increased parallel computation, other functions, communication, or memory, as well as increased <a href="Input/output" title="Input/output">input/output</a> capabilities. This comes at the cost of general-purpose utility.

</p>

<div class="mw-heading mw-heading3"><h3 id="Emerging_hardware_architectures">Emerging hardware architectures</h3></div>

<p>Greater RTL customization of hardware designs allows emerging architectures such as <a href="In-memory_processing" title="In-memory processing">in-memory computing</a>, <a href="Transport_triggered_architecture" title="Transport triggered architecture">transport triggered architectures</a> (TTA) and <a href="Network_on_a_chip" title="Network on a chip">networks-on-chip</a> (NoC) to further benefit from increased <a href="Locality_of_reference" title="Locality of reference">locality</a> of data to execution context, thereby reducing computing and communication latency between modules and functional units.

</p><p>Custom hardware is limited in parallel processing capability only by the area and <a href="Logic_block" title="Logic block">logic blocks</a> available on the <a href="Die_(integrated_circuit)" title="Die (integrated circuit)">integrated circuit die</a>.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> Therefore, hardware is much more free to offer <a href="Massively_parallel" title="Massively parallel">massive parallelism</a> than software on general-purpose processors, offering a possibility of implementing the <a href="Parallel_RAM" title="Parallel RAM">parallel random-access machine</a> (PRAM) model.

</p><p>It is common to build <a href="Multi-core_processor" title="Multi-core processor">multicore</a> and <a href="Manycore_processor" title="Manycore processor">manycore</a> processing units out of <a href="Soft_microprocessor" title="Soft microprocessor">microprocessor IP core schematics</a> on a single FPGA or ASIC.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> Similarly, specialized functional units can be composed in parallel, as <a href="Parallel_processing_(DSP_implementation)" title="Parallel processing (DSP implementation)">in digital signal processing</a>, without being embedded in a processor <a href="Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP core</a>. Therefore, hardware acceleration is often employed for repetitive, fixed tasks involving little <a href="Conditional_(computer_programming)" title="Conditional (computer programming)">conditional branching</a>, especially on large amounts of data. This is how <a href="Nvidia" title="Nvidia">Nvidia</a>'s <a href="CUDA" title="CUDA">CUDA</a> line of GPUs are implemented.

</p>

<div class="mw-heading mw-heading3"><h3 id="Implementation_metrics">Implementation metrics</h3></div>

<p>As device mobility has increased, new metrics have been developed that measure the relative performance of specific acceleration protocols, considering characteristics such as physical hardware dimensions, power consumption, and operations throughput. These can be summarized into three categories: task efficiency, implementation efficiency, and flexibility. Appropriate metrics consider the area of the hardware along with both the corresponding operations throughput and energy consumed.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup>

</p>

<div class="mw-heading mw-heading2"><h2 id="Applications">Applications</h2></div>

<p>Examples of hardware acceleration include <a href="Bit_blit" title="Bit blit">bit blit</a> acceleration functionality in graphics processing units (GPUs), use of <a href="Memristor" title="Memristor">memristors</a> for accelerating <a href="Artificial_neural_network" class="mw-redirect" title="Artificial neural network">neural networks</a>, and <a href="Regular_expression" title="Regular expression">regular expression</a> hardware acceleration for <a href="Anti-spam_techniques" title="Anti-spam techniques">spam control</a> in the <a href="Server_(computing)" title="Server (computing)">server</a> industry, intended to prevent <a href="ReDoS" title="ReDoS">regular expression denial of service</a> (ReDoS) attacks.<sup id="cite_ref-wellho_17-0" class="reference"><a href="#cite_note-wellho-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> The hardware that performs the acceleration may be part of a general-purpose CPU, or a separate unit called a hardware accelerator, though they are usually referred to with a more specific term, such as 3D accelerator, or <a href="Cryptographic_accelerator" title="Cryptographic accelerator">cryptographic accelerator</a>.

</p><p>Traditionally, processors were sequential (instructions are executed one by one), and were designed to run general purpose algorithms controlled by <a href="Instruction_fetch" class="mw-redirect" title="Instruction fetch">instruction fetch</a> (for example, moving temporary results <a href="Load/store_architecture" class="mw-redirect" title="Load/store architecture">to and from</a> a <a href="Register_file" title="Register file">register file</a>). Hardware accelerators improve the execution of a specific algorithm by allowing greater <a href="Concurrency_(computer_science)" title="Concurrency (computer science)">concurrency</a>, having specific <a href="Datapath" title="Datapath">datapaths</a> for their <a href="Temporary_variable" title="Temporary variable">temporary variables</a>, and reducing the overhead of instruction control in the fetch-decode-execute cycle.

</p><p>Modern processors are <a href="Multi-core_processor" title="Multi-core processor">multi-core</a> and often feature parallel "single-instruction; multiple data" (<a href="Single_instruction%2C_multiple_data" title="Single instruction, multiple data">SIMD</a>) units. Such units can be integrated withint the <a href="Central_processing_unit" title="Central processing unit">CPU</a> or offered by additional components as the <a href="AI_engine" title="AI engine">AMD AI engines</a>.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> Even so, hardware acceleration still yields benefits. Hardware acceleration is suitable for any computation-intensive algorithm which is executed frequently in a task or program. Depending upon the granularity, hardware acceleration can vary from a small functional unit, to a large functional block (like <a href="Motion_estimation" title="Motion estimation">motion estimation</a> in <a href="MPEG-2" title="MPEG-2">MPEG-2</a>).

</p>

<div class="mw-heading mw-heading2"><h2 id="Hardware_acceleration_units_by_application">Hardware acceleration units by application</h2></div>

</caption>

<th>Application

</th>

<th>Hardware accelerator

</th>

<th>Acronym

</th></tr>

<tr>

<td>

</td>

<td>

</td>

<td>

</td></tr>

<tr>

<td><a href="Computer_graphics" title="Computer graphics">Computer graphics</a>

<ul><li>General-purpose computing</li>

<li>GP computing, on Nvidia graphics cards</li>

<li><a href="Ray_tracing_(graphics)" title="Ray tracing (graphics)">Ray tracing</a></li>

<li><a href="Video_codec" title="Video codec">Video codec</a></li></ul>

</td>

<td>Graphics processing unit

<ul><li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">General-purpose computing on GPU</a></li>

<li><a href="CUDA" title="CUDA">CUDA</a> architecture</li>

<li><a href="Ray-tracing_hardware" title="Ray-tracing hardware">Ray-tracing hardware</a></li>

<li>Various video acceleration hardware</li></ul>

</td>

<td>GPU

<ul><li>GPGPU</li>

</td></tr>

<tr>

<td>

</td>

<td>

</td>

<td>

</td></tr>

<tr>

<td><a href="Digital_signal_processing" title="Digital signal processing">Digital signal processing</a>

</td>

<td><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processor</a>

</td>

<td>DSP

</td></tr>

<tr>

<td><a href="Analog_signal_processing" title="Analog signal processing">Analog signal processing</a>

</td>

<td><a href="Field-programmable_analog_array" title="Field-programmable analog array">Field-programmable analog array</a>

<ul><li><a href="Field-programmable_RF" title="Field-programmable RF">Field-programmable RF</a></li></ul>

</td>

<td>FPAA

</td></tr>

<tr>

<td><a href="Image_processing" class="mw-redirect" title="Image processing">Image processing</a>

</td>

<td><a href="Webcam" title="Webcam">Webcam</a> or <a href="Image_processor" title="Image processor">image processor</a>

</td>

<td>IPU

</td></tr>

<tr>

<td><a href="Audio_signal_processing" title="Audio signal processing">Sound processing</a>

</td>

<td><a href="Sound_card" title="Sound card">Sound card</a> and <a href="Sound_card_mixer" title="Sound card mixer">sound card mixer</a>

</td>

<td>N/A

</td></tr>

<tr>

<td><a href="Computer_network" title="Computer network">Computer networking</a>

<li>Input/output</li></ul>

</td>

<td><a href="Network_processor" title="Network processor">Network processor</a> and <a href="Network_interface_controller" title="Network interface controller">network interface controller</a>

<ul><li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a></li>

<li><a href="TCP_offload_engine" title="TCP offload engine">TCP offload engine</a></li>

<li><a href="IPsec" title="IPsec">IPsec</a> offload<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup></li>

<li><a href="I/O_Acceleration_Technology" title="I/O Acceleration Technology">I/O Acceleration Technology</a></li></ul>

</td>

<td>NPU and NIC

<li>TCPOE or TOE</li>

</td></tr>

<tr>

<td><a href="Cryptography" title="Cryptography">Cryptography</a>

<ul><li><a href="Encryption" title="Encryption">Encryption</a>

<li><a href="Cryptanalysis" title="Cryptanalysis">Attack</a></li>

<li><a href="Random_number_generation" title="Random number generation">Random number generation</a></li></ul>

</td>

<td><a href="Cryptographic_accelerator" title="Cryptographic accelerator">Cryptographic accelerator</a> and <a href="Secure_cryptoprocessor" title="Secure cryptoprocessor">secure cryptoprocessor</a>

<ul><li><a href="Hardware-based_encryption" title="Hardware-based encryption">Hardware-based encryption</a>

<ul><li><a href="AES_instruction_set" title="AES instruction set">AES instruction set</a></li>

<li><a href="TLS_acceleration" title="TLS acceleration">SSL acceleration</a></li></ul></li>

<li><a href="Custom_hardware_attack" title="Custom hardware attack">Custom hardware attack</a></li>

<li><a href="Hardware_random_number_generator" title="Hardware random number generator">Hardware random number generator</a></li></ul>

</td>

<td>N/A

</td></tr>

<tr>

<td><a href="Artificial_intelligence" title="Artificial intelligence">Artificial intelligence</a>

<ul><li><a href="Machine_vision" title="Machine vision">Machine vision</a>/<a href="Computer_vision" title="Computer vision">computer vision</a></li>

<li><a href="Artificial_neural_network" class="mw-redirect" title="Artificial neural network">Neural networks</a></li>

<li><a href="Brain_simulation" title="Brain simulation">Brain simulation</a></li></ul>

</td>

<td><a href="AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerator</a>

<ul><li><a href="Vision_processing_unit" title="Vision processing unit">Vision processing unit</a></li>

<li><a href="Physical_neural_network" title="Physical neural network">Physical neural network</a></li>

<li><a href="Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic engineering</a></li></ul>

</td>

<td>N/A

</td></tr>

<tr>

<td><a href="Multilinear_algebra" title="Multilinear algebra">Multilinear algebra</a>

</td>

<td><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor processing unit</a>

</td>

<td>TPU

</td></tr>

<tr>

<td><a href="Computational_physics" title="Computational physics">Physics simulation</a>

</td>

<td><a href="Physics_processing_unit" title="Physics processing unit">Physics processing unit</a>

</td>

<td>PPU

</td></tr>

<tr>

<td><a href="Regular_expression" title="Regular expression">Regular expressions</a><sup id="cite_ref-wellho_17-1" class="reference"><a href="#cite_note-wellho-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup>

</td>

<td>Regular expression coprocessor

</td>

<td>N/A

</td></tr>

<tr>

<td><a href="Data_compression" title="Data compression">Data compression</a><sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup>

</td>

<td>Data compression accelerator

</td>

<td>N/A

</td></tr>

<tr>

<td>In-memory processing

</td>

<td>Network on a chip and <a href="Systolic_array" title="Systolic array">Systolic array</a>

</td>

<td>NoC; N/A

</td></tr>

<tr>

<td><a href="Data_processing" title="Data processing">Data processing</a>

</td>

<td><a href="Data_processing_unit" title="Data processing unit">Data processing unit</a>

</td>

<td>DPU

</td></tr>

<tr>

<td>Any computing task

</td>

<td>Computer hardware

<ul><li>Field-programmable gate arrays<sup id="cite_ref-Farabet_21-0" class="reference"><a href="#cite_note-Farabet-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup></li>

<li>Application-specific integrated circuits<sup id="cite_ref-Farabet_21-1" class="reference"><a href="#cite_note-Farabet-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup></li>

<li><a href="Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic devices</a></li>

<li>Systems-on-Chip

<ul><li><a href="Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multi-processor system-on-chip</a></li>

<li><a href="Programmable_system-on-chip" class="mw-redirect" title="Programmable system-on-chip">Programmable system-on-chip</a></li></ul></li></ul>

</td>

<td>HW (sometimes)

<li>SoC

<ul><li>MPSoC</li>

</td></tr></tbody></table>

<ul><li><a href="Coprocessor" title="Coprocessor">Coprocessor</a></li>

<li><a href="DirectX_Video_Acceleration" title="DirectX Video Acceleration">DirectX Video Acceleration</a> (DXVA)</li>

<li><a href="Direct_memory_access" title="Direct memory access">Direct memory access</a> (DMA)</li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a>

<li><a href="Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li>

<li><a href="Flynn's_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a> of parallel <a href="Computer_architecture" title="Computer architecture">computer architectures</a>

<ul><li><a href="Single_instruction%2C_multiple_data" title="Single instruction, multiple data">Single instruction, multiple data</a> (SIMD)</li>

<li><a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">Single instruction, multiple threads</a> (SIMT)</li>

<li><a href="Multiple_instruction%2C_multiple_data" title="Multiple instruction, multiple data">Multiple instructions, multiple data</a> (MIMD)</li></ul></li>

<li><a href="Computer_for_operations_with_functions" title="Computer for operations with functions">Computer for operations with functions</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><span class="noviewer" typeof="mw:File"></span> Media related to <a href="https://commons.wikimedia.org/wiki/Category:Hardware_acceleration" class="extiw external" title="commons:Category:Hardware acceleration">Hardware acceleration</a> at Wikimedia Commons</li></ul>

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</style><div id="Hardware_acceleration129" style="font-size:114%;margin:0 4em"></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Model_of_computation" title="Model of computation">Theory</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Universal_Turing_machine" title="Universal Turing machine">Universal Turing machine</a></li>

<li><a href="Parallel_computing" title="Parallel computing">Parallel computing</a></li>

<li><a href="Distributed_computing" title="Distributed computing">Distributed computing</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li>

<li><a href="DirectX_Video_Acceleration" title="DirectX Video Acceleration">DirectX</a></li></ul></li>

<li><a href="Sound_card" title="Sound card">Audio</a></li>

<li><a href="Digital_signal_processor" title="Digital signal processor">Digital signal processing</a></li>

<li><a href="Hardware_random_number_generator" title="Hardware random number generator">Hardware random number generation</a></li>

<li><a href="Neural_processing_unit" title="Neural processing unit">Neural processing unit</a></li>

<li><a href="Cryptographic_accelerator" title="Cryptographic accelerator">Cryptography</a>

<li><a href="Vision_processing_unit" title="Vision processing unit">Machine vision</a></li>

<li><a href="Custom_hardware_attack" title="Custom hardware attack">Custom hardware attack</a>

<ul><li><a href="Scrypt" title="Scrypt">scrypt</a></li></ul></li>

<li><a href="Network_processor" title="Network processor">Networking</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Implementations</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a>

<li><a href="System_on_a_chip" title="System on a chip">System on a chip</a>

<ul><li><a href="Network_on_a_chip" title="Network on a chip">Network on a chip</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Computer_architecture" title="Computer architecture">Architectures</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li>

<li><a href="Transport_triggered_architecture" title="Transport triggered architecture">Transport triggered</a></li>

<li><a href="Multi-core_processor" title="Multi-core processor">Multicore</a></li>

<li><a href="Manycore_processor" title="Manycore processor">Manycore</a></li>

<li><a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous</a></li>

<li><a href="In-memory_processing" title="In-memory processing">In-memory computing</a></li>

<li><a href="Systolic_array" title="Systolic array">Systolic array</a></li>

<li><a href="Neuromorphic_computing" title="Neuromorphic computing">Neuromorphic</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic</a></li>

<li><a href="Processor_(computing)" title="Processor (computing)">Processor</a>

<ul><li><a href="Processor_design" title="Processor design">design</a></li>

<li><a href="Microprocessor_chronology" title="Microprocessor chronology">chronology</a></li></ul></li>

<li><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></li>

<li><a href="Virtualization" title="Virtualization">Virtualization</a>

<ul><li><a href="Hardware_emulation" title="Hardware emulation">Hardware emulation</a></li></ul></li>

<li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Embedded_system" title="Embedded system">Embedded systems</a></li></ul>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Graphics_processing_unit85" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Graphics_processing_unit85" style="font-size:114%;margin:0 4em"><a href="Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">GPU</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Desktop</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel</a>

<li><a href="List_of_Nvidia_graphics_processing_units" title="List of Nvidia graphics processing units">Nvidia</a>

<ul><li><a href="GeForce" title="GeForce">GeForce</a></li>

<li><a href="Quadro" title="Quadro">Quadro</a></li>

<li><a href="Nvidia_Tesla" title="Nvidia Tesla">Tesla</a></li>

<li><a href="Nvidia_Tegra" class="mw-redirect" title="Nvidia Tegra">Tegra</a></li></ul></li>

<ul><li><a href="Radeon" title="Radeon">Radeon</a></li>

<li><a href="Radeon_Pro" title="Radeon Pro">Radeon Pro</a></li>

<li><a href="AMD_Instinct" title="AMD Instinct">Instinct</a></li></ul></li>

<li><a href="Matrox" title="Matrox">Matrox</a></li>

<li><a href="InfiniteReality" title="InfiniteReality">InfiniteReality</a></li>

<li><a href="Comparison_of_3dfx_graphics_processing_units" class="mw-redirect" title="Comparison of 3dfx graphics processing units">3dfx Voodoo</a></li>

<li><a href="Glaze3D" title="Glaze3D">Glaze3D</a></li>

<li><a href="Apple_silicon" title="Apple silicon">Apple silicon</a></li>

<li><a href="Jingjia_Micro" title="Jingjia Micro">Jingjia Micro</a></li>

<li><a href="Tseng_Labs" title="Tseng Labs">Tseng Labs</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Mobile</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Adreno" title="Adreno">Adreno</a></li>

<li><a href="Apple_silicon" title="Apple silicon">Apple silicon</a></li>

<li><a href="PowerVR" title="PowerVR">PowerVR</a></li>

<li><a href="VideoCore" title="VideoCore">VideoCore</a></li>

<li><a href="Vivante_Corporation" title="Vivante Corporation">Vivante</a></li>

<li><a href="Imageon" title="Imageon">Imageon</a></li>

<li><a href="Intel_2700G" title="Intel 2700G">Intel 2700G</a></li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Architecture</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Compute_kernel" title="Compute kernel">Compute kernel</a></li>

<li><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a>

<li><a href="FinFET" class="mw-redirect" title="FinFET">FinFET</a></li>

<li><a href="MOSFET" title="MOSFET">MOSFET</a></li></ul></li>

<li><a href="Graphics_pipeline" title="Graphics pipeline">Graphics pipeline</a>

<ul><li><a href="Geometry_pipelines" title="Geometry pipelines">Geometry</a></li>

<li><a href="Vertex_pipeline" title="Vertex pipeline">Vertex</a></li></ul></li>

<li><a href="High-dynamic-range_rendering" title="High-dynamic-range rendering">HDR rendering</a></li>

<li><a href="Rasterisation" title="Rasterisation">Rasterisation</a>

<ul><li><a href="Shading" title="Shading">Shading</a></li></ul></li>

<li><a href="Ray-tracing_hardware" title="Ray-tracing hardware">Ray-tracing</a></li>

<li><a href="Tessellation_(computer_graphics)" title="Tessellation (computer graphics)">Tessellation</a></li>

<li><a href="Tiled_rendering" title="Tiled rendering">Tiled rendering</a></li>

<li><a href="Unified_shader_model" title="Unified shader model">Unified shader model</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Blitter" title="Blitter">Blitter</a></li>

<li><a href="Geometry_processing" title="Geometry processing">Geometry processor</a></li>

<li><a href="Input%E2%80%93output_memory_management_unit" title="Input–output memory management unit">Input–output memory management unit</a></li>

<li><a href="Render_output_unit" title="Render output unit">Render output unit</a></li>

<li><a href="Shader" title="Shader">Shader unit</a></li>

<li><a href="Stream_processing" title="Stream processing">Stream processor</a></li>

<li><a href="Tensor" title="Tensor">Tensor unit</a></li>

<li><a href="Texture_mapping_unit" title="Texture mapping unit">Texture mapping unit</a></li>

<li><a href="Video_display_controller" title="Video display controller">Video display controller</a></li>

<li><a href="Video_processing_unit" class="mw-redirect" title="Video processing unit">Video processing unit</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Memory</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Framebuffer" title="Framebuffer">Framebuffer</a></li>

<li><a href="SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a>

<li><a href="Memory_bandwidth" title="Memory bandwidth">Memory bandwidth</a></li>

<li><a href="Memory_controller" title="Memory controller">Memory controller</a></li>

<li><a href="Shared_graphics_memory" title="Shared graphics memory">Shared graphics memory</a></li>

<li><a href="Texture_memory" title="Texture memory">Texture memory</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Form factor</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Video_card" class="mw-redirect" title="Video card">Discrete graphics</a>

<ul><li><a href="GPU_cluster" title="GPU cluster">Clustering</a></li>

<li><a href="GPU_switching" title="GPU switching">Switching</a></li></ul></li>

<li><a href="External_GPU" class="mw-redirect" title="External GPU">External graphics</a></li>

<li><a href="Integrated_graphics" class="mw-redirect" title="Integrated graphics">Integrated graphics</a></li>

<li><a href="System_on_a_chip" title="System on a chip">System on a chip</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Performance</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Clock_rate" title="Clock rate">Clock rate</a></li>

<li><a href="Computer_display_standard" class="mw-redirect" title="Computer display standard">Display resolution</a></li>

<li><a href="Fillrate" title="Fillrate">Fillrate</a>

<ul><li><a href="Gigapixel_image" title="Gigapixel image">Pixel/s</a></li>

<li><a href="Texel_(graphics)" title="Texel (graphics)">Texel/s</a></li></ul></li>

<li><a href="Frame_rate" title="Frame rate">Frame rate</a></li>

<li><a href="Performance_per_watt" title="Performance per watt">Performance per watt</a></li>

<li><a href="Transistor_count" title="Transistor count">Transistor count</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Misc</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Scrolling" title="Scrolling">Scrolling</a></li>

<li><a href="Sprite_(computer_graphics)" title="Sprite (computer graphics)">Sprite</a></li>

<li><a href="Texture_mapping" title="Texture mapping">Texture</a></li></ul></li>

<li><a href="General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li>

<li><a href="Graphics_library" title="Graphics library">Graphics library</a></li>

<li><a href="Digital_image_processing" title="Digital image processing">Image processing</a>

<ul><li><a href="Image_compression" title="Image compression">Compression</a></li></ul></li>

<li><a href="Parallel_computing" title="Parallel computing">Parallel computing</a></li>

<li><a href="Vector_processor" title="Vector processor">Vector processor</a></li>

<li><a href="Video_coding_format" title="Video coding format">Video coding</a>

<ul><li><a href="Video_codec" title="Video codec">Codec</a></li></ul></li>

</div></td></tr></tbody></table></div>

<div class="navbox-styles"></div><div role="navigation" class="navbox" aria-labelledby="Digital_electronics118" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div id="Digital_electronics118" style="font-size:114%;margin:0 4em"><a href="Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Transistor" title="Transistor">Transistor</a></li>

<li><a href="Resistor" title="Resistor">Resistor</a></li>

<li><a href="Inductor" title="Inductor">Inductor</a></li>

<li><a href="Capacitor" title="Capacitor">Capacitor</a></li>

<li><a href="Printed_electronics" title="Printed electronics">Printed electronics</a></li>

<li><a href="Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li>

<li><a href="Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li>

<li><a href="Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li>

<li><a href="Combinational_logic" title="Combinational logic">Combinational logic</a></li>

<li><a href="Sequential_logic" title="Sequential logic">Sequential logic</a></li>

<li><a href="Logic_gate" title="Logic gate">Logic gate</a></li>

<li><a href="Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li>

<li><a href="Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li>

<li><a href="Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li>

<li><a href="Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li>

<li><a href="Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li>

<li><a href="Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li>

<li><a href="Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li>

<li><a href="Macrocell_array" title="Macrocell array">Macrocell array</a></li>

<li><a href="Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li>

<li><a href="Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li>

<li><a href="Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li>

<li><a href="Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li>

<li><a href="Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li>

<li><a href="Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li>

<li><a href="Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li>

<li><a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li>

<li><a href="Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Digital_signal" title="Digital signal">Digital signal</a></li>

<li><a href="Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li>

<li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li>

<li><a href="Computer_architecture" title="Computer architecture">Computer architecture</a></li>

<li><a href="Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a>

<ul><li><a href="Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li>

<li><a href="Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li>

<li><a href="Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li>

<li><a href="Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li>

<li><a href="Place_and_route" title="Place and route">Place and route</a>

<ul><li><a href="Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li>

<li><a href="Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li>

<li><a href="Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li>

<li><a href="Register-transfer_level" title="Register-transfer level">Register-transfer level</a>

<ul><li><a href="Hardware_description_language" title="Hardware description language">Hardware description language</a></li>

<li><a href="High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li>

<li><a href="Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li>

<li><a href="Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li>

<li><a href="Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li>

<li><a href="Finite-state_machine" title="Finite-state machine">Finite-state machine</a>

<ul><li><a href="Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Computer_hardware" title="Computer hardware">Computer hardware</a>

<li><a href="Digital_audio" title="Digital audio">Digital audio</a>

<ul><li><a href="Digital_radio" title="Digital radio">radio</a></li></ul></li>

<li><a href="Digital_photography" title="Digital photography">Digital photography</a></li>

<li><a href="Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li>

<li><a href="Digital_video" title="Digital video">Digital video</a>

<ul><li><a href="Digital_cinematography" title="Digital cinematography">cinematography</a></li>

<li><a href="Digital_television" title="Digital television">television</a></li></ul></li>

<li><a href="Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li>

<li><a href="Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul>

</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2025-07-30" href="https://en.wikipedia.org/wiki/?title=Hardware_acceleration&oldid=1303346118">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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